The present invention relates to programmable circuits, and more particularly to programmable circuits that can be used to enable or disable electrical signals.
Fuse-programmable circuits have been used to disable select signals to salvage memories having defective memory arrays. More particularly, when a memory die is manufactured and tested and defects are discovered in one of the memory arrays on the die but another one of the memory arrays is defect-free, the die can be salvaged by disabling the defective memory array. This is desirable, in particular, when the defects cannot be fixed by redundant circuitry. The defective memory array is disabled by disabling a select signal S (FIG. 1A) which selects the array in response to address signals. In FIG. 1A, select signal S is an output of an address decoder NAND gate 110. The output of address NAND gate 110 is connected to an input IN of a disabling circuit 114. Circuit 114 includes a transmission gate 118 containing NMOS transistor Q1 and PMOS transistor Q2. These transistors are connected in parallel between input IN and output OUT of circuit 114. The signal S' on output OUT is coupled to the memory array (not shown) through inverter amplifier 122. The gate of NMOS transistor Q1 is connected to output OUTH of fuse programmable latch 130 (FIG. 1B). The gate of PMOS transistor Q2 is connected to complementary output OUTL of latch 130. Output OUTL is also connected to the gate of NMOS transistor Q3 of circuit 114. Transistor Q3 is connected between output OUT and ground.
Latch 130 is described in U.S. Pat. No. 5,440,246 "Programmable Circuit with Fusible Latch" issued Aug. 8, 1995 on an invention of M. Murray et al. In this latch, fuse F1 is connected between a power supply voltage VCC and output OUTH. NMOS transistor Q4 is connected between output OUTH and ground. Fuse F2 is connected between output OUTL and ground. PMOS transistor Q5 is connected between output OUTL and power supply voltage VCC. The gate of transistor Q4 is connected to output OUTL. The gate of transistor Q5 is connected to output OUTH.
When fuses F1 and F2 are intact, the latch output OUTH is high (VCC) and the latch output OUTL is low (ground). When fuses F1 and F2 are blown, output OUTH is low and output OUTL is high.
If the memory array selectable by signal S is not to be disabled (because the memory array has no defects or at least no defects that are not fixed by redundant circuitry), fuses F1 and F2 are left intact. Hence, transmission gate 118 is open, coupling the select signal S to the terminal OUT. Transistor Q3 is off. Therefore, signal S' is enabled to select or deselect the memory array in response to address signals in a normal manner.
If the memory array must be permanently disabled, fuses F1 and F2 are blown. As a result, transmission gate 118 is closed, and transistor Q3 pulls the output OUT to ground.
The same circuit 114, 130 of FIGS. 1A, 1B can be used to always select a non-defective memory array when a defective memory array is disabled.
FIG. 2 illustrates an alternate signal-disabling circuit 210 which can be used instead of circuit 114. Like circuit 114, circuit 210 is controlled by a latch 130 (not shown in FIG. 2). Circuit 210 is identical to circuit 114 except that the transistor Q3 is replaced by a PMOS transistor Q6 connected between output OUT and power supply voltage VCC. The gate of transistor Q6 is connected to output OUTH of latch 130. When fuses F1 and F2 are intact, transmission gate 118 of circuit 210 couples the terminal IN to the terminal OUT, and transistor Q6 is off. When fuses F1 and F2 are blown, transmission gate 118 decouples terminal OUT from terminal IN, and transistor Q6 pulls the output OUT to VCC.
When the die is manufactured, it is not known in advance whether any given memory array will have to be permanently enabled or disabled. Therefore, circuitry is needed that can be programmed to permanently fix the array select signal at either the high or the low voltage level. Such circuitry is shown in FIG. 3. In FIG. 3, circuits 114, 210 are connected in series between an input terminal 310 receiving the select signal S and an output terminal 320 which provides the signal S'. Circuit 114 is controlled by a latch 130.1 which is a copy of the latch 130 (FIG. 1B). Circuit 210 is controlled by another latch 130.2 which is a copy of the latch 130. If the fuses of latches 130.1, 130.2 are intact, then circuits 114, 210 couple the output 320 to the input 310. If the fuses of latch 130.1 are blown and the fuses of latch 130.2 are intact, output 320 is pulled to ground. If the fuses of latch 130.1 are intact and the fuses of latch 130.2 are blown, output 320 is pulled to VCC.
It is desirable to provide a simpler and faster circuit than the circuit of FIG. 3. More particularly, the circuit of FIG. 3 includes 10 transistors (three transistors in each of circuits 114, 210 and two transistors in each of latches 130.1, 130.2). Further, the circuit has a delay through two transmission gates from input 310 to output 320. It is desirable to simplify the circuit and reduce the circuit delay.